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lt 3959 1 3959fa for more information www.linear.com/lt3959 typical application features description wide input voltage range boost/sepic/inverting converter with 6a, 40v switch 2.5v to 24v input, 12v output sepic converter excellent for automotive 12v post regulator applications n wide v in range: 1.6v (2.5v start-up) to 40v n positive or negative output voltage programming with a single feedback pin n pgood output voltage status report n internal 6a/40v power switch n programmable soft-start n programmable operating frequency (100 khz to 1 mhz ) with one external resistor n synchronizable to an external clock n low shutdown current < 1a n intv cc regulator supplied from v in or drive n programmable input undervoltage lockout with hysteresis n thermally enhanced qfn (5mm 6mm) and tssop packages n automotive n telecom n industrial l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7825665. the lt ? 3959 is a wide input range, current mode, dc/dc controller which is capable of regulating either positive or negative output voltages from a single feedback pin. it can be configured as a boost, sepic or inverting converter. it features an internal low side n-channel mosfet rated for 6 a at 40 v and driven from an internal regulated sup - ply provided from v in or drive. the fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. the operating frequency of lt3959 can be set over a 100 khz to 1 mhz range with an external resistor, or can be synchronized to an external clock using the sync pin. the lt3959 features soft-start and frequency foldback functions to limit inductor current during start-up and output short-circuit. a window comparator on the fbx pin reports via the pgood pin, providing output voltage status indication. efficiency vs output current output current (ma) 0 efficiency (%) 90 95 100 600 1000 3959 ta01b 85 200 400 800 8075 70 65 60 v in = 12v lt3959 v in v in 2.5v to 24v c in 22f50v 2 27.4k 300khz 4.7f 50v gnd drive fbx sgnd intv cc en_uvlopgood sync tie to sgnd if not used rtss v c l1a l1b gndk sw 124k 121k 0.1f 7.5k 22nf 105k 150k 4.7f v out 12v500ma at v in = 2.5v 1.5a at v in > 8v 3959 ta01a 15.8k c out 47f16v 2 downloaded from: http:///
lt 3959 2 3959fa for more information www.linear.com/lt3959 pin configuration absolute maximum ratings v in ............................................................................ 40 v en / uvlo ( note 2) ..................................................... 40 v drive ....................................................................... 40 v pgood ...................................................................... 40 v sw ............................................................................ 40 v intv cc ........................................................................ 8v sync .......................................................................... 8v (note 1) v c , ss ......................................................................... 3v rt ............................................................................ 1.5 v gnd , gndk to sgnd ............................................. 0.3 v fbx ................................................................. C3 v to 3v operating junction temperature range ( note 3) lt 3959 e/ lt 3959 i .............................. C40 c to 125 c storage temperature range .................. C65 c to 125 c 12 13 14 top view uhema package 36-lead (5mm 6mm) plastic qfn 15 16 17 36 35 34 33 32 31 30 21 23 24 25 27 28 8 6 4 3 2 1 ncnc nc sgnd nc swsw nc drivev in en/uvlosgnd nc sw sw intv cc pgoodsync rt ss fbx v c gndk gndgnd gnd gnd gnd 20 9 10 37 sgnd 38 sw t jmax =125c, ja = 42c/w, jc = 3c/w exposed pad (pin 37) is sgnd, must be soldered to sgnd plane exposed pad (pin 38) is sw, must be soldered to sw plane 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 3837 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 ncnc nc v c fbx ss rt sync pgood sgnd nc sw ncnc sw nc gndk gndgnd ncnc nc nc en/uvlo v in drive intv cc ncsgnd nc sw nc nc sw nc gnd gnd gnd 39 sgnd 40 sw t jmax =125c, ja = 42c/w, jc = 3c/w exposed pad (pin 39) is sgnd, must be soldered to sgnd plane exposed pad (pin 40) is sw, must be soldered to sw plane downloaded from: http:///
lt 3959 3 3959fa for more information www.linear.com/lt3959 electrical characteristics parameter conditions min typ max units v in operating voltage l 1.6 40 v v in start-up voltage r t = 27.4k, fbx = 0 l 2.5 2.65 v v in shutdown i q en/uvlo < 0.4v en/uvlo = 1.15v 0.1 1 6 a a v in operating i q 350 450 a drive shutdown quiescent current en/uvlo < 0.4v en/uvlo = 1.15v 0.1 0.1 1 2 a a drive quiescent current (not switching) r t = 27.4k, drive = 6v 2.0 2.5 ma sw pin current limit l 6.0 7.0 8.0 a sw pin on voltage i sw = 3a 100 mv sw pin leakage current sw = 40v 5 a error amplifier fbx regulation voltage (v fbx(reg) ) fbx > 0v fbx < 0v l l 1.580 C0.815 1.6 C0.80 1.620 C0.785 v v fbx pin input current fbx = 1.6v fbx = C0.8v C10 80 130 10 na na transconductance g m (?i vc /?v fbx ) fbx = v fbx(reg) 240 s v c output impedance 5 m fbx line regulation [?v fbx(reg) /(?v in ? v fbx(reg) )] 1.6v < v in < 40v, fbx >0 1.6v < v in < 40v, fbx <0 0.02 0.02 0.05 0.05 %/v %/v v c source current fbx = 0v, v c = 1.3v C13 a v c sink current fbx = 1.7v, v c = 1.3v fbx = C0.85v, v c = 1.3v 13 10 a a oscillator switching frequency r t = 27.4k to sgnd, v fbx = 1.6v r t = 86.6k to sgnd, v fbx = 1.6v r t = 6.81k to sgnd, v fbx = 1.6v l 250 300 100 1000 340 khz khz khz r t voltage fbx = 1.6v, C0.8v 1.13 v sw minimum off-time 150 200 ns sw minimum on-time 150 200 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 12v, en/uvlo = 12v, intv cc = 4.75v, unless otherwise noted. order information lead free finish tape and reel part marking* package description temperature range lt3959euhe#pbf lt3959euhe#trpbf 3959 36-lead (5mm 6mm) plastic qfn C40c to 125c lt3959iuhe#pbf lt3959iuhe#trpbf 3959 36-lead (5mm 6mm) plastic qfn C40c to 125c lt3959efe#pbf lt3959efe#trpbf lt3959fe 38-lead plastic tssop C40c to 125c lt3959ife#pbf lt3959ife#trpbf lt3959fe 38-lead plastic tssop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
lt 3959 4 3959fa for more information www.linear.com/lt3959 parameter conditions min typ max units sync input low l 0.4 v sync input high l 1.5 v ss pull-up current ss = 0v, current out of pin l C14 C10.5 C7 a low dropout regulators (drive ldo and v in ldo) drive ldo regulation voltage drive = 6v, not switching l 4.6 4.75 4.9 v v in ldo regulation voltage drive = 0v, not switching l 3.6 3.75 3.9 v drive ldo current limit intv cc = 4v 60 ma v in ldo current limit drive = 0v, intv cc = 3v 60 ma drive ldo load regulation (?v intvcc /v intvcc ) 0 < i intvcc < 20ma, drive = 6v C1 C0.6 % v in ldo load regulation (?v intvcc /v intvcc ) drive = 0v, 0 < i intvcc < 20ma C1 C0.6 % drive ldo line regulation [?v intvcc /(v intvcc ? ? v in )] 1.6v < v in < 40v, drive = 6v 0.03 0.07 %/v v in ldo line regulation [?v intvcc /(v intvcc ? ? v in )] drive = 0v, 5v < v in < 40v 0.03 0.07 %/v drive ldo dropout voltage (v drive C v intvcc ) drive = 4v, i intvcc = 20ma l 190 400 mv v in ldo dropout voltage (v in C v intvcc ) v in = 3v, drive = 0v, i intvcc = 20ma l 190 400 mv intv cc undervoltage lockout threshold falling l 1.85 2.0 2.15 v intv cc undervoltage lockout threshold rising l 2.15 2.3 2.45 v intv cc current in shutdown en/uvlo = 0v 25 a logic en/uvlo threshold voltage falling l 1.17 1.22 1.27 v en/uvlo threshold voltage rising hysteresis 20 mv en/uvlo input low voltage i vin < 1a 0.4 v en/uvlo pin bias current low en/uvlo = 1.15v 1.8 2.2 2.6 a en/uvlo pin bias current high en/uvlo = 1.30v 10 100 na fbx power good threshold voltage fbx > 0v, pgood falling fbx < 0v, pgood falling v fbx ( reg ) C 0.08 v fbx ( reg ) + 0.04 v v fbx overvoltage threshold fbx > 0v, pgood rising fbx < 0v, pgood rising v fbx ( reg ) + 0.12 v fbx ( reg ) C 0.06 v v pgood output low (v ol ) i pgood = 250a 210 300 mv pgood leakage current pgood = 40v 1 a intv cc minimum voltage to enable pgood function l 2.5 2.7 2.9 v intv cc minimum voltage to enable sync function l 2.5 2.7 2.9 v electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 12v, en/uvlo = 12v, intv cc = 4.75v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: for v in below 4v, the en/uvlo pin must not exceed v in for proper operation. note 3: the lt3959e is guaranteed to meet performance specifications from the 0c to 125c operating junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3959i is guaranteed over the full C40c to 125c operating junction temperature range. note 4: the lt3959 is tested in a feedback loop which servos v fbx to the reference voltages (1.6v and C0.8v) with the v c pin forced to 1.3v. downloaded from: http:///
lt 3959 5 3959fa for more information www.linear.com/lt3959 typical performance characteristics dynamic quiescent current vs switching frequency r t vs switching frequency normalized switching frequency vs fbx voltage switching frequency vs temperature sw current limit vs temperature sw current limit vs duty cycle fbx positive regulation voltage vs temperature fbx negative regulation voltage vs temperature quiescent current vs temperature switching frequency (khz) 0 i q (ma) 15 20 25 600 1000 3959 g04 10 200 400 800 5 0 i q (v in ) i q (drive) drive = 6v switching frequency (khz) 0 r t (k) 6050 8070 100 90 600 1000 3959 g05 4030 200 100 400 800 700 300 500 900 2010 0 fbx voltage (v) C0.8 normalized frequency (%) 8060 120100 1.6 3959 g06 40 C0.4 0.8 0 0.4 1.2 20 0 temperature (c) C50 fbx regulation voltage (v) 1.61 1.62 0 125 3959 g01 1.60 C25 25 50 75 100 1.59 1.58 temperature (c) C50 fbx regulation voltage (v) C0.79 C0.78 0 125 3959 g02 C0.80 C25 25 50 75 100 C0.81 C0.82 temperature (c) C50 i q (ma) 2.42.0 1.6 1.2 0.4 0.80.0 0 125 3959 g03 C25 25 50 75 100 i q (v in ) v in = 12v drive = 6v i q (drive) temperature (c) C50 sw current limit (a) 7.67.4 7.2 7.0 6.8 6.6 6.4 0 125 3959 g08 C25 25 50 75 100 duty cycle (%) 0 sw current limit (a) 6.55.5 7.0 8.07.5 100 3959 g09 6.0 20 60 40 80 5.0 temperature (c) C50 switching frequency (khz) 350325 300 275 250 0 125 3959 g07 C25 25 50 75 100 t a = 25c, unless otherwise noted. downloaded from: http:///
lt 3959 6 3959fa for more information www.linear.com/lt3959 typical performance characteristics intv cc vs temperature intv cc load regulation intv cc line regulation intv cc dropout voltage vs current, temperature internal switch on-resistance vs temperature internal switch on-resistance vs intv cc en/uvlo threshold vs temperature sw minimum on- and off-times vs temperature en/uvlo hysteresis current vs temperature temperature (c) C50 on-resistance (m) 6040 5030 125 100 75 50 3959 g17 0 C25 25 20 intc cc (v) 2 on-resistance (m) 5045 40 35 5 4 4.5 3959 g18 3 2.5 3.5 30 temperature (c) C50 en/uvlo voltage (v) 1.271.25 1.23 1.21 1.19 1.17 0 125 3959 g10 C25 25 50 75 100 en/uvlo rising en/uvlo falling temperature (c) C50 en/uvlo (a) 2.42.2 2.0 1.8 1.6 0 125 3959 g12 C25 25 50 75 100 intv cc load (ma) 0 intv cc voltage (v) 4 5 4.5 25 3959 g14 3.5 5 15 10 20 3 drive ldo v in ldo (drive = 0v) intv cc load (ma) 0 dropout voltage (mv) 200 400300 25 3959 g16 100 5 15 10 20 0 v in = 12v drive = 4v 125c 25c C40c temperature (c) C50 intv cc (v) 5.04.8 4.6 4.4 4.0 3.8 4.23.6 0 125 3959 g13 C25 25 50 75 100 drive ldo v in ldo t a = 25c, unless otherwise noted. temperature (c) C50 minimum on/off time (ns) 200190 180 170 160 150 140 130 0 125 3959 g11 C25 25 50 75 100 minimumoff time minimumon time v in (v) 0 intv cc voltage (v) 5.04.5 4.0 45 35 40 3959 g15 3.5 5 15 10 20 30 25 3.0 drive ldo drive = 6v drive = 0v v in ldo downloaded from: http:///
lt 3959 7 3959fa for more information www.linear.com/lt3959 pin functions drive: drive ldo supply pin. this pin can be connected to either v in or a quasi-regulated voltage supply such as a dc converter output. this pin must be bypassed to gnd with a minimum of 1 f capacitor placed close to the pin. tie this pin to v in if not used. en/uvlo: shutdown and undervoltage detect pin. an accurate 1.22 v ( nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. rising hysteresis is generated by the external resistor divider and an accurate internal 2.2 a pull-down current. an undervoltage condition resets soft- start. tie to 0.4 v, or less, to disable the device and reduce v in quiescent current below 1a. fbx: voltage regulation feedback pin for positive or negative outputs. connect this pin to a resistor divider between the output and sgnd. fbx is the input of two error amplifiersone configured to regulate a positive output; the other, a negative output. depending upon topology selected, switching causes the output to ramp positive or negative. the appropriate amplifier takes control while the other becomes inactive. additionally fbx is input for two window comparators that indicate through the pgood pin when the output is within 5% of the regulation volt- ages. fbx also modulates the switching frequency during start-up and fault conditions when fbx is close to sgnd. gnd: source terminal of switch and the gnd input to the switch current comparator . gndk: kelvin connection pin between gnd and sgnd. kelvin connect this pin to the sgnd plane close to the ic. see the board layout section. intv cc : regulated supply for internal loads and gate driver. regulated to 4.75 v if powered from drive or regulated to 3.75 v if powered from v in . the intv cc pin must be bypassed to sgnd with a minimum of 4.7 f capacitor placed close to the pin. nc: no internal connection. leave these pins open or connect them to the adjacent pins. pgood : output ready status pin. an open-collector pull down on pgood asserts when intv cc is greater than 2.7v and the fbx voltage is within 5% (80 mv if v fbx = 1.6v or 40mv if v fbx = C0.8v) of the regulation voltage. rt : switching frequency adjustment pin. set the frequency using a resistor to sgnd. do not leave the rt pin open. sgnd: signal ground. must be soldered directly to the signal ground plane. connect to ground terminal of: ex- ternal resistor dividers for fbx and en/uvlo; capacitors for intv cc , ss, and v c ; and resistor r t . ss: soft-start pin. this pin modulates compensation pin voltage ( v c ) clamp. the soft-start interval is set with an external capacitor. the pin has a 10 a ( typical) pull-up current source to an internal 2.5 v rail. the soft-start pin is reset to sgnd by an en/uvlo undervoltage condition, an intv cc undervoltage condition or an internal thermal lockout.sw: drain of internal power n-channel mosfet. sync: frequency synchronization pin. used to synchronize the internal oscillator to an outside clock. if this feature is used, an r t resistor should be chosen to program a switch - ing frequency 20% slower than sync pulse frequency. tie the sync pin to sgnd if this feature is not used. this signal is ignored during fb frequency foldback or when intv cc is less than 2.7v. v in : supply pin for internal leads and the v in ldo regu- lator of intv cc . must be locally bypassed to gnd with a minimum of 1f capacitor placed close to this pin.v c : error amplifier compensation pin. used to stabilize the voltage loop with an external rc network. place com- pensation components between the v c pin and sgnd. downloaded from: http:///
lt 3959 8 3959fa for more information www.linear.com/lt3959 block diagram figure 1. lt3959 block diagram working as a sepic converter (shown for qfn package) 1.22v 1.2v 2.5v c in c vcc intv cc drive v in r sense v isense i s1 2.2a 28 36 8, 9, 20, 21 30 25 en/uvlo bandgap reference tsd ~165?c a10 q3 v c sgnd v c bg_low uvlo otp i s2 10a i s3 c c1 r pg v in c c2 r c driver slope gnd 13, 1415, 16 17 sw m1 45mv sr1 +? ramp generator + ? r q s 2.5v ss c ss sync freqfoldback 1.25v fbx pgood fbx q4 1.6v ?0.8v +? +? 31 35 32 34 + ? +? ramp pwmcomparator frequency foldback 100khz ~ 1mhz oscillator r1 r2 l2 fbx d1 c dc v out c out ? 3759 f01 a1a2 1.72v ?0.86v + ? + ? a11a12 +? a3 1.25v freqprog ? ++ q1 rt r t a4 a5 a6 g5 g6 a7 q2 g4 r3 r4 v in 27 internal bias generator drive ldo current limit internal bias current limit v in ldo a8 + ? g8 1.52v ?0.76v + ? + ? a13a14 g7 2.7v a15 + ? g2 g1 ? l1 bg sgnd gndk 4, 24 33 12 sgnd sgnd sgnd (qfn package) downloaded from: http:///
lt 3959 9 3959fa for more information www.linear.com/lt3959 applications information main control loop the lt3959 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. operation can be best understood by referring to the block diagram in figure 1. the start of each oscillator cycle sets the sr latch ( sr1) and turns on the internal power mosfet switch m 1 through driver g2. the switch current flows through the internal current sensing resistor r sense and generates a voltage proportional to the switch current. this current sense voltage v isense ( amplified by a5) is added to a stabilizing slope compensation ramp and the resulting sum ( slope) is fed into the positive terminal of the pwm comparator a7. when slope exceeds the level at the negative input of a7 (v c pin), sr1 is reset, turning off the power switch. the level at the negative input of a7 is set by the error amplifier a 1 ( or a2) and is an amplified version of the difference between the feedback voltage ( fbx pin) and the reference voltage (1.6 v or C0.8 v, depending on the configuration). in this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. the lt3959 has a switch current limit function. the cur- rent sense voltage is input to the current limit comparator a6. if the sense voltage is higher than the sense current limit threshold v sense(max) (45 mv, typical), a6 will reset sr1 and turn off m1 immediately. the lt3959 is capable of generating either positive or negative output voltage with a single fbx pin. it can be configured as a boost or sepic converter to generate positive output voltage, or as an inverting converter to generate negative output voltage. when configured as a sepic converter, as shown in figure 1, the fbx pin is pulled up to the internal bias voltage of 1.6 v by a volt- age divider ( r1 and r2) connected from v out to sgnd. comparator a2 becomes inactive and comparator a1 performs the inverting amplification from fbx to v c . when the lt3959 is in an inverting configuration, the fbx pin is pulled down to C0.8 v by a voltage divider connected from v out to sgnd. comparator a1 becomes inactive and comparator a2 performs the noninverting amplification from fbx to v c . the lt3959 has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. an overvoltage comparator a 11 ( with 40 mv hysteresis) senses when the fbx pin voltage exceeds the positive regulated voltage (1.6 v) by 7.5% and turns off m1. similarly, an overvoltage comparator a 12 ( with 20 mv hysteresis) senses when the fbx pin voltage exceeds the negative regulated voltage (C0.8 v) by 7.5% and turns off m1. both reset pulses are sent to the main rs latch (sr1) through g6 and g5. the internal power mosfet switch m1 is actively held off for the duration of an output overvoltage condition. programming turn-on and turn-off thresholds with en/uvlo pin the en/uvlo pin controls whether the lt3959 is enabled or is in shutdown state. a micropower 1.22 v reference, a comparator a10 and controllable current source i s1 allow the user to accurately program the supply voltage at which the ic turns on and off. the falling value can be accurately set by the resistor dividers r3 and r4. when en/uvlo is above 0.7 v, and below the 1.22 v threshold, the small pull-down current source i s1 (typical 2.2a) is active. the purpose of this current is to allow the user to program the rising hysteresis. the block diagram of the comparator and the external resistors is shown in figure 1. the typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: v vin(falling) = 1.22 ? (r3 + r4) r4 v vin(rising) = 2.2a ? r3 + v in(falling) for applications where the en/uvlo pin is only used as a logic input, the en/uvlo pin can be connected directly to the input voltage v in for always-on operation. downloaded from: http:///
lt 3959 10 3959fa for more information www.linear.com/lt3959 intv cc low dropout voltage regulators the lt3959 features two internal low dropout ( ldo) volt- age regulators ( v in ldo and drive ldo) powered from different supplies ( v in and drive respectively). both ldo s regulate the internal intv cc supply which powers the gate driver and the internal loads, as shown in figure 1. both regulators are designed so that current does not flow from intv cc to the ldo input under a reverse bias condition. drive ldo regulates the intv cc to 4.75 v, while v in ldo regulates the intv cc to 3.75 v. v in ldo is turned off when the intv cc voltage is greater than 3.75 v ( typical). both ldos can be turned off if the intv cc pin is driven by a supply of 4.75 v or higher but less than 8 v ( the intv cc maximum voltage rating is 8 v). a table of the ldo sup- ply and output voltage combination is shown in table 1. table 1. ldo s supply and output voltage combination ( assuming that the ldo dropout voltage is 0.15v) supply voltages ldo output ldo status (note 7) v in drive intv cc v in 3.9v v drive < v in v in C 0.15v #1 is on v drive = v in v in C 0.15v #1 #2 are on v in < v drive < 4.9v v drive C 0.15v #2 is on 4.9v v drive 40v 4.75v #2 is on 3.9v < v in 40v v drive < 3.9v 3.75v #1 is on v drive = 3.9v 3.75v #1 #2 are on 3.9 v < v drive < 4.9 v v drive C 0.15v #2 is on 4.9v v drive 40v 4.75v #2 is on note 7: #1 is v in ldo and #2 is drive ldo the drive pin provides flexibility to power the gate driver and the internal loads from a supply that is available only when the switcher is enabled and running . if not used, the drive pin should be tied to v in . the intv cc pin must be bypassed to sgnd immediately adjacent to the intv cc pin with a minimum of 4.7 f ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate driver. operating frequency and synchronization the choice of operating frequency may be determined by on-chip power dissipation, otherwise it is a trade-off between efficiency and component size. low frequency op - eration improves efficiency by reducing gate drive current and internal mosfet and diode switching losses. however , lower frequency operation requires a physically larger inductor. switching frequency also has implications for loop compensation. the lt3959 uses a constant - frequency architecture that can be programmed over a 100 khz to 1mhz range with a single external resistor from the rt pin to sgnd, as shown in figure 1. the rt pin must have an external resistor to sgnd for proper operation of the lt3959. a table for selecting the value of r t for a given operating frequency is shown in table 2. table 2. timing resistor (r t ) value oscillator frequency (khz) r t (k) 100 86.6 200 41.2 300 27.4 400 21.0 500 16.5 600 13.7 700 11.5 800 9.76 900 8.45 1000 6.81 the switching frequency of the lt3959 can be synchro- nized to the positive edge of an external clock source. by providing a digital clock signal into the sync pin, the lt3959 will operate at the sync clock frequency. if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than sync pulse frequency. the sync pulse should have a minimum pulse width of 200 ns. tie the sync pin to sgnd if this feature is not used. applications information downloaded from: http:///
lt 3959 11 3959fa for more information www.linear.com/lt3959 duty cycle consideration switching duty cycle is a key variable defining converter operation. as such, its limits must be considered. minimum on-time is the smallest time duration that the lt3959 is capable of turning on the internal power mosfet. this time is generally about 150 ns ( typical ) ( see minimum on-time in the electrical characteristics table). in each switching cycle, the lt3959 keeps the power switch off for at least 150ns ( typical ) ( see minimum off-time in the electrical characteristics table). the minimum on-time and minimum off-time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate:minimum duty cycle = minimum on-time ? frequency maximum duty cycle = 1 C ( minimum off - time ? frequency ) programming the output voltage the output voltage ( v out ) is set by a resistor divider, as shown in figure 1. the positive v out and negative v out are set by the following equations: v out(positive) = 1.6v ? 1 + r2 r1 ? ? ? ? ? ? v out(negative) = C0.8v ? 1 + r2 r1 ?? ? ?? ? the resistors r1 and r2 are typically chosen so that the error caused by the current flowing into the fbx pin dur- ing normal operation is less than 1% ( this translates to a maximum value of r1 at about 121k).soft-start the lt3959 contains several features to limit peak switch currents and output voltage ( v out ) overshoot during start-up or recovery from a fault condition. the primary purpose of these features is to prevent damage to external components or the load. high peak switch currents during start-up may occur in switching regulators. since v out is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. a large surge current may cause inductor saturation or power switch failure. lt3959 addresses this mechanism with the ss pin. as shown in figure 1, the ss pin reduces the internal power mosfet current by pulling down the v c pin through q2. in this way the ss allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. besides start - up, soft - start can also be triggered by intv cc undervoltage lockout and / or thermal lockout, which causes the lt3959 to stop switching immediately. the ss pin will be discharged by q3. when all faults are cleared and the ss pin has been discharged below 0.2 v, a 10 a current source i s2 starts charging the ss pin, initiating a soft-start operation. the soft-start interval is set by the soft-start capacitor selection according to the equation: t ss = c ss ? 1.25v 10a fbx frequency foldback when v out is very low during start-up or a short-circuit fault on the output, the switching regulator must operate at low duty cycles to maintain the power switch current within the current limit range, since the inductor current decay rate is very low during switch off time. the minimum on-time limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switching frequency. so, the switch current will keep increasing through each switch cycle, exceeding the programmed current limit. to prevent the switch peak currents from exceeding the programmed value, the lt3959 contains a frequency foldback function to reduce the switching frequency when the fbx voltage is low ( see the normal - ized switching frequency vs fbx graph in the typical performance characteristics section). applications information downloaded from: http:///
lt 3959 12 3959fa for more information www.linear.com/lt3959 some frequency foldback waveforms are shown in the typical applications section. the frequency foldback func- tion prevents i l from exceeding the programmed limits because of the minimum on-time.during frequency foldback, external clock synchronization is disabled to allow the frequency reducing operation to function properly.loop compensation loop compensation determines the stability and transient performance. the lt3959 uses current mode control to regulate the output which simplifies loop compensation. the optimum values depend on the converter topology, the component values and the operating conditions ( including the input voltage, load current, etc.). to compensate the feedback loop of the lt3959, a series resistor-capacitor network is usually connected from the v c pin to sgnd. figure 1 shows the typical v c compensation network. for most applications, the capacitor should be in the range of 470pf to 22 nf, and the resistor should be in the range of 5k to 50 k. a small capacitor is often connected in paral - lel with the rc compensation network to attenuate the v c voltage ripple induced from the output voltage ripple through the internal error amplifier. the parallel capacitor usually ranges in value from 10 pf to 100 pf. a practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. stability should then be checked across all operating conditions, including load current, input voltage and temperature.the internal power switch current for control and protection, the lt3959 measures the internal power mosfet current by using a sense resistor (r sense ) between gnd and the mosfet source. figure 2 shows a typical wave-form of the internal switch current (i sw ). due to the current limit ( minimum 6 a ) of the internal power switch, the lt3959 should be used in the applications that the switch peak current i sw(peak) during steady state normal operation is lower than 6 a by a sufficient margin (10% or higher is recommended).it is recommended to measure the ic temperature in steady state to verify that the junction temperature limit (125 c) is not exceeded. a low switching frequency may be required to ensure t j(max) does not exceed 125c. if lt3959 die temperature reaches thermal lockout threshold at 165 c ( typical), the ic will initiate several protective actions. the power switch will be turned off. a soft-start operation will be triggered. the ic will be en- abled again when the junction temperature has dropped by 5c (nominal).applica tion circuits the lt3959 can be configured as different topologies. the design procedure for component selection differs somewhat between these topologies. the first topology to be analyzed will be the boost converter, followed by sepic and inverting converters. figure 2. the sw current during a switching cycle applications information 3959 f02 i sw(peak) ? i sw i sw t dt s t s downloaded from: http:///
lt 3959 13 3959fa for more information www.linear.com/lt3959 boost converter: switch duty cycle and frequency the lt3959 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. remember that boost con - verters are not short-circuit protected. under a shorted output condition, the inductor current is limited only by the input supply capability. for applications requiring a step-up converter that is short-circuit protected, please refer to the applications information section covering sepic converters.the conversion ratio as a function of duty cycle is: v out v in = 1 1 ? d in continuous conduction mode (ccm). for a boost converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage ( v out ) and the input voltage ( v in ). the maximum duty cycle ( d max ) occurs when the converter has the minimum input voltage: d max = v out ? v in(min) v out the alternative to ccm, discontinuous conduction mode (dcm) is not limited by duty cycle to provide high con- version ratios at a given frequency. the price one pays is reduced efficiency and substantially higher switching current.boost converter: maximum output current capability and inductor selection for the boost topology, the maximum average inductor current is: i l(max) = i o(max) ? 1 1 ? d max applications information due to the current limit of its internal power switch, the lt3959 should be used in a boost converter whose maxi- mum output current ( i o(max) ) is less than the maximum output current capability by a sufficient margin (10% or higher is recommended): i o(max) < v in(min) v out ? (6a C 0.5 ? ? i sw ) the inductor ripple current ?i sw has a direct effect on the choice of the inductor value and the converters maximum output current capability. choosing smaller values of ?i sw increases output current capability, but requires large inductances and reduces the current loop gain ( the converter will approach voltage mode). accepting larger values of ?i sw provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses, and reduces output current capability. given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined using the following equation: l = v in(min) ? i sw ? f osc ? d max the peak inductor current is the switch current limit (7 a typical), and the rms inductor current is approximately equal to i l(max) . the user should choose the inductors having sufficient saturation and rms current ratings.boost converter: output diode selection to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. the average forward current in normal operation is equal to the output current. downloaded from: http:///
lt 3959 14 3959fa for more information www.linear.com/lt3959 it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out by a safety margin ( a 10 v safety margin is usually sufficient).the power dissipated by the diode is: p d = i o(max) ? v d where v d is diodes forward voltage drop, and the diode junction temperature is: t j = t a + p d ? r j a the r ja to be used in this equation normally includes the r jc for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating . boost converter: output capacitor selection contributions of esr ( equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. the effect of these three parameters ( esr, esl and bulk c ) on the output voltage ripple waveform for a typical boost converter is illustrated in figure 3. the choice of component(s) begins with the maximum acceptable ripple voltage ( expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step ? v esr and charging/discharging ?v cout . for the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ? v esr and ? v cout . this percentage ripple will change, depending on the requirements of the application, applications information and the following equations can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr cout 0.01 ? v out i d(peak) for the bulk c component, which also contributes 1% to the total ripple: c out i o(max) 0.01 ? v out ? ? osc the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 3. the rms ripple current rating of the output capacitor can be determined using the following equation: i rms(cout) i o(max) ? d max 1 ? d max multiple capacitors are often paralleled to meet esr requirements. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the required rms current rating. additional ceramic capaci - tors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output.boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and the input current wave- form is continuous. the input voltage source impedance determines the size of the input capacitor, which is typi- cally in the range of 10f to 100f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a boost converter is: i rms(cin) = 0.3 ? ? i l v out (ac) t on ? v esr ringing due tototal inductance (board + cap) ? v cout 3959 f03 t off figure 3. the output ripple waveform of a boost converter downloaded from: http:///
lt 3959 15 3959fa for more information www.linear.com/lt3959 sepic converter applications the lt3959 can be configured as a sepic ( single-ended primary inductance converter), as shown in figure 1. this topology allows for the input to be higher, equal, or lower than the desired output voltage. the conversion ratio as a function of duty cycle is: v out + v d v in = d 1 ? d in continuous conduction mode (ccm).in a sepic converter, no dc path exists between the input and output. this is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. sepic converter: switch duty cycle and frequency for a sepic converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage ( v out ), the input voltage ( v in ) and diode forward voltage (v d ). the maximum duty cycle ( d max ) occurs when the converter has the minimum input voltage: d max = v out + v d v in(min) + v out + v d sepic converter: the maximum output current capability and inductor selection as shown in figure 1, the sepic converter contains two inductors: l 1 and l 2. l 1 and l 2 can be independent, but can also be wound on the same core, since identical voltages are applied to l1 and l2 throughout the switching cycle. for the sepic topology, the current through l1 is the converter input current. based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of l1 and l2 are: i l1(max) = i in(max) = i o(max) ? d max 1C d max i l2(max) = i o(max) due to the current limit of its internal power switch, the lt3959 should be used in a sepic converter whose maximum output current ( io ( max)) is less than the output current capability by a sufficient margin (10% or higher is recommended): i o(max) < (1Cd max ) ? (6 a C 0.5 ? ? i sw ) the inductor ripple currents ?i l1 and ?i l2 are identical: ? i l1 = ?i l2 = 0.5 ? ? i sw the inductor ripple current ? i sw has a direct effect on the choice of the inductor value and the converters maximum output current capability. choosing smaller values of ? i sw requires large inductances and reduces the current loop gain ( the converter will approach voltage mode). accepting larger values of ? i sw allows the use of low inductances, but results in higher input current ripple and greater core losses and reduces output current capability. given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value ( l 1 and l 2 are independent) of the sepic converter can be determined using the following equation: l1 = l2 = v in(min) 0.5 ? ? i sw ? ? osc ? d max for most sepic applications, the equal inductor values will fall in the range of 1h to 100h. by making l 1 = l 2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2l, due to mutual inductance: l = v in(min) ? i sw ? ? osc ? d max this maintains the same ripple current and energy storage in the inductors. the peak inductor currents are: i l1(peak) = i l1(max) + 0.5 ? ? i l1 i l2(peak) = i l2(max) + 0.5 ? ? i l2 the maximum rms inductor currents are approximately equal to the maximum average inductor currents. applications information downloaded from: http:///
lt 3959 16 3959fa for more information www.linear.com/lt3959 based on the preceding equations, the user should choose the inductors having sufficient saturation and rms cur- rent ratings.sepic converter : output diode selection to maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. the average forward current in normal operation is equal to the output current. it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out + v in(max) by a safety margin (a 10v safety margin is usually sufficient).the power dissipated by the diode is: p d = i o(max) ? v d where v d is diodes forward voltage drop, and the diode junction temperature is: t j = t a + p d ? r ja the r ja used in this equation normally includes the r jc for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. sepic converter: output and input capacitor selection the selections of the output and input capacitors of the sepic converter are similar to those of the boost converter . please refer to the boost converter, output capacitor selection and boost converter, input capacitor selection sections.sepic converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor ( c dc , as shown in figure 1) should be larger than the maximum input voltage: v cdc > v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately C i o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? v out + v d v in(min) a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . inverting converter applications the lt3959 can be configured as a dual-inductor inverting topology, as shown in figure 4. the v out to v in ratio is: v out C v d v in = C d 1 ? d in continuous conduction mode (ccm). applications information c dc v in c in l1 d1 c out v out 3959 f04 + gnd sw lt3959 l2 + C + C + figure 4. a simplified inverting converter inverting converter: switch duty cycle and frequency for an inverting converter operating in ccm, the duty cycle of the main switch can be calculated based on the negative output voltage ( v out ) and the input voltage ( v in ). the maximum duty cycle ( d max ) occurs when the converter has the minimum input voltage: d max = v out C v d v out C v d C v in(min) downloaded from: http:///
lt 3959 17 3959fa for more information www.linear.com/lt3959 applications information inverting converter: output diode and input capacitor selections the selections of the inductor, output diode and input capacitor of an inverting converter are similar to those of the sepic converter. please refer to the corresponding sepic converter sections.inverting converter: output capacitor selection the inverting converter requires much smaller output capacitors than those of the boost and sepic converters for similar output ripple. this is due to the fact that, in the inverting converter, the inductor l2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. the output ripple voltage is produced by the ripple current of l2 flowing through the esr and bulk capacitance of the output capacitor: ? v out(p ? p) = ? i l2 ? esr cout + 1 8 ? f osc ? c out ? ? ? ? ? ? after specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. the esr can be minimized by using high quality x5r or x7r dielectric ceramic capacitors. in many applications, ceramic capacitors are sufficient to limit the output volt - age ripple. the rms ripple current rating of the output capacitor needs to be greater than: i rms(cout) > 0.3 ? ? i l2 inverting converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor ( c dc , as shown in figure 4) should be larger than the maximum input voltage minus the output voltage ( negative voltage): v cdc > v in(max) C v out c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately C i o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? d max 1C d max a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . board layout the high power and high speed operation of the lt3959 demands careful attention to board layout and component placement. careful attention must be paid to the internal power dissipation of the lt3959 at high input voltages, high switching frequencies, and high internal power switch currents to ensure that a junction temperature of 125 c is not exceeded. this is especially important when operating at high ambient temperatures. exposed pads on the bot - tom of the package are sgnd and sw terminals of the ic, and must be soldered to a sgnd ground plane and a sw plane respectively. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into the copper planes with as much as area as possible.to prevent radiation and high frequency resonance prob - lems, proper layout of the components connected to the ic is essential, especially the power paths with higher di / dt . the following high di / dt loops of different topologies should be kept as tight as possible to reduce inductive ringing : ? in boost configuration, the high di/dt loop contains the output capacitor, the internal power mosfet and the schottky diode. ? in sepic configuration, the high di/dt loop contains the internal power mosfet, output capacitor, schottky diode and the coupling capacitor. ? in inverting configuration, the high di/dt loop contains internal power mosfet, schottky diode and the coupling capacitor. downloaded from: http:///
lt 3959 18 3959fa for more information www.linear.com/lt3959 applications information check the stress on the internal power mosfet by mea- suring the sw-to-gnd voltage directly across the ic ter- minals. make sure the inductive ringing does not exceed the maximum rating of the internal power mosfet (40 v). the small-signal components should be placed away from high frequency switching nodes. for optimum load regula - tion and true remote sensing, the top of the output voltage sensing resistor divider should connect independently to the top of the output capacitor ( kelvin connection), staying away from any high dv/dt traces. place the divider resis- tors near the lt3959 in order to keep the high impedance fbx node short. figure 5 shows the suggested layout of the 2.5 v to 8 v input , 12 v output boost converter in the typical applica - tion section. downloaded from: http:///
lt 3959 19 3959fa for more information www.linear.com/lt3959 applications information figure 5. suggested layout of the 2.5v to 8v input. 12v output boost converter in the typical application section (shown for qfn package) 3959 f05 lt3959 3738 10 via to v out r1 r2 c ss c vcc r t r5 r c c c r3 r4 d1 sw sgnd l1 c out c out c in gnd v out v in via to v out via to v out via to v in vias to sgnd ground planevias to sw plane 36 35 34 33 32 31 30 21 23 24 25 27 2820 12 13 14 15 16 17 8 6 4 3 2 19 downloaded from: http:///
lt 3959 20 3959fa for more information www.linear.com/lt3959 typical applications 2.5v to 5v input, C5v output inverting converter efficiency vs output current gnd lt3959 v in v in 2.5v to 5v c in 47f10v x5r c dc 4.7f, 25v x7r 1f16v x5r drive fbx intv cc ss rt en/uvlosync pgoodsgnd v c l1b l1a gndk sw 22k 9.09k 10nf 0.1f 27.4k 300khz 124k 121k c vcc 4.7f10v x5r v out C5v1a 3959 ta02 d2 d1 84.5k15.8k l1a, l1b: coiltronics drq127-3r3d1: vishay 6cwq03fn d2: philips pmeg2005ej c out 47f10v x5r 2 output current (ma) 0 efficiency (%) 100 600 3759 ta02a 200 400 1000 800 7060 80 9050 v in = 5v downloaded from: http:///
lt 3959 21 3959fa for more information www.linear.com/lt3959 typical applications 2.5v to 24v input, 12v output sepic converter drive lt3959 l1a l1b v in v c sw d1 l1a, l1b: coiltronics drq127-150d1: vishay 6cwq06fn gnd fbx rtss intv cc en/uvlosync tie to sgnd ifnot used pgood sgnd 3959 ta03 124k 121k 150k 7.5k 4.7f 27.4k300khz 22nf 0.1f 105k 15.8k gndk 4.7f 50v v out 12v500ma at v in = 2.5v 1.5a at v in > 8v v in 2.5v to 24v c in 22f50v 2 c out1 47f16v x5r 2 ? ? efficiency vs output current load step response at v in = 12v frequency foldback waveforms when output short-circuits output current (ma) 0 efficiency (%) 90 100 800 3759 ta03b 80 400 200 600 1000 65 70 75 85 9560 v in = 12v 500s/div v out 500mv/div (ac) i out 500ma/div 0.2a 0.8a 3959 ta03c 500s/div v out 10v/div v sw 20v/div i l1a+l1b 2.5a/div 3959 ta03d downloaded from: http:///
lt 3959 22 3959fa for more information www.linear.com/lt3959 typical applications 2.5v to 8v input, 12v led driver efficiency vs v in 3959 ta04 drive lt3959 l1 8.2h v in sw l1: toko 962bs-br2md1: vishay siliconix 20bq030 dz1: central semiconductor cmhz5252b gnd fbx rt ss intv cc en/uvlo pgoodsync sgnd r2121k v c d1 dz124v gndk r1124k r t 27.4k 300khz c vcc 4.7f10v x5r c ss 0.1f r c 4.99k c c 22nf r43.48k r50.5 c out 22f16v x5r 2 12v leds500ma v out v in 2.5v to 8v c in 22f16v x5r r37.68k v in (v) 2 efficiency (%) 90 94 7 3959 ta04b 86 5 4 3 6 8 84 88 9282 downloaded from: http:///
lt 3959 23 3959fa for more information www.linear.com/lt3959 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 6.00 0.10 note:1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side pin 1top mark (note 6) 0.40 0.10 1 36 35 30 31 32 33 34 2820 21 23 24 25 27 23 4 6 8 9 10 12 13 14 15 16 17 bottom view?exposed pad 2.00 ref 1.50 ref 0.75 0.05 r = 0.125typ r = 0.10 typ pin 1 notchr = 0.30 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uhe36(28)ma) qfn 0112 rev d recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.10 0.05 5.50 0.05 package outline 1.88 0.10 1.53 0.10 2.00 ref 1.50 ref 5.10 0.05 6.50 0.05 uhe package variation: uhe36(28)ma 36(28)-lead plastic qfn (5mm 6mm) (reference ltc dwg # 05-08-1836 rev d) 3.00 0.10 3.00 0.10 0.12 0.10 1.88 0.05 1.53 0.05 3.00 0.05 3.00 0.05 0.48 0.05 0.12 0.05 0.48 0.10 0.25 0.05 0.50 bsc 10 1 2 3 4 6 8 9 17 20 21 23 24 25 27 28 3031 32 33 34 35 36 12 13 14 15 16 5. exposed pad shall be solder plated6. shaded area is only a reference for pin 1 location on the top and bottom of package downloaded from: http:///
lt 3959 24 3959fa for more information www.linear.com/lt3959 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 4.75 (.187) ref fe38 (ac) tssop rev ? 0311 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout apply solder mask to areas that are not soldered 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.70 1.60 0.45 millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1779 rev ?) split exposed pad variation ac 0.45 (.018) ref 2.70 (.106) ref 1.60 (.063) 2.38 (.094) 2.74 (.108) ref downloaded from: http:///
lt 3959 25 3959fa for more information www.linear.com/lt3959 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 06/13 added tssop-28 package 1, 2, 7, 24 downloaded from: http:///
lt 3959 26 3959fa for more information www.linear.com/lt3959 ? linear technology corporation 2012 lt 0613 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3959 related parts typical application part number description comments lt3957 boost, flyback, sepic and inverting converter with 5a, 40v switch 3v v in 40v, 100khz to 1mhz programmable operation frequency, 5mm 6mm qfn package lt3958 boost, flyback, sepic and inverting converter with 3.3a, 84v switch 5v v in 80v, 100khz to 1mhz programmable operation frequency, 5mm 6mm qfn package lt3759 boost, flyback, sepic and inverting controller 1.6v v in 42v, 100khz to 1mhz programmable operation frequency, msop-12e package lt3758 boost, flyback, sepic and inverting controller 5.5v v in 100v, 100khz to 1mhz programmable operation frequency, 3mm 3mm dfn-10 and msop-10e packages lt3757 boost, flyback, sepic and inverting controller 2.9v v in 40v, 100khz to 1mhz programmable operation frequency, 3mm 3mm dfn-10 and msop-10e packages lt3748 100v isolated flyback controller 5v v in 100v, no opto flyback , msop-16 with high voltage spacing lt3798 off-line isolated no opto-coupler flyback controller with active pfc v in and v out limited only by external components 2.5v to 8v input, 12v output boost converter drive lt3959 l1 10h v in sw l1: coiltronics dr125-100d1: vishay siliconix 20bq030 gnd fbx rt ss intv cc en/uvlo pgoodsync sgnd r4121k v c 3959 ta05 d1 gndk r3124k r547k r t 27.4k 300khz c vcc 4.7f10v x5r c ss 0.22f r c 3.4k c c 22nf r2105k r115.8k c out 47f16v x5r 2 v out 12v500ma, 2.5v v in < 5v 1a, 5v v in 8v v in 2.5v to 8v c in 22f16v x5r efficiency vs output current load step response at v in = 8v output current (ma) 0 efficiency (%) 85 95 100 600 800 3759 ta05b 75 200 400 1000 80 90 70 v in = 5v 500s/div v out 500mv/div (ac) i out 500ma/div 0.2a 0.8a 3959 ta05c downloaded from: http:///

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